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AS8510 data acquisition devi ce for battery sensors www.austriamicrosystems.com/AS8510 revision 3.4 1 - 46 datasheet 1 general description the AS8510 is a virtually offset free, low noise, two channel measurement device. it is tailored to accurately measure battery current from ma range up to ka range in conjunction with a 100 shunt resistor in series with the battery rail. through the second measurement channel it enables capture of, either battery voltage synchronous with the current measurement, or, measure the analog output of an internal or external temperature sensor. both channels are matched and can either measure small signals up to 160 mv versus ground, through programmable gain amplifier or larger signals in the 0 to 1v range without the amplifier. after analog to digital conversion and digital filtering, the resulting 16-bit digital words are accessible through 4-wire standard serial interface.the device includes a number of additional features explained in the next section. 2 key features 3.3v supply voltage two high resolution 16 bit ? a/d converters programmable sampling to enable data throughputs from less than 1hz to 8khz zero offset for both channels independent control of data rate on both channels precision, low noise, programmable gain amplifiers for both channels with gains 5, 25, 40, 100 to support wide dynamic ranges. option for multiplexing either one differential input, or two single ended inputs or the internal temperature sensor on one channel programmable current source for external temperature sensor connectable to any of the inputs high precision and high stability 1.2v reference voltage source digital signal processing with filter options for both channels four operating modes providing - continuous data acquisition (or) - periodic single-shot acquisition, (or) - continuous acquisition on threshold crossing of programmed current levels (or) - a combination of the above on chip high-precision 4mhz rc oscillator or option for external clock -40oc to +125oc ambient operation aec - q100 automotive qualified internal chip id for full traceability ssop-20 pin package 3 applications the AS8510 is ideal for shunt based batteries sensor. for high-side current sensing, the input signal may be conditioned using austriamicrosystems device as8525 before applying to this device. vbat_in dvdd sdo sdi sclk cs avdd int clk dvss rshh rshl etr vcm ets chop_clk men vbat_gnd internal temperature sensor pga pga 16-bit sigma-delta adc 16-bit sigma-delta adc serial interface oscillators fir / ma analog common mode chopper mux and chopper bandgap reference avss ref AS8510 prog-cur source figure 1. AS8510 block diagram
www.austriamicrosystems.com/AS8510 revision 3.4 2 - 46 AS8510 datasheet - contents contents 1 general description ......................................................................................................... ......................................................... 1 2 key features................................................................................................................ ............................................................. 1 3 applications................................................................................................................ ............................................................... 1 4 pin assignments ............................................................................................................. .......................................................... 4 4.1 pin descriptions.......................................................................................................... .......................................................................... 4 5 absolute maximum ratings .................................................................................................... .................................................. 6 6 electrical characteristics.................................................................................................. ......................................................... 7 6.1 operating conditions...................................................................................................... ...................................................................... 7 6.2 dc/ac characteristics for digital inputs and outputs ...................................................................... .................................................... 7 6.3 detailed system and block specifications .................................................................................. ......................................................... 8 6.3.1 electrical system specific ations ........................................................................................ .......................................................... 8 6.4 current measurement ranges (across 100 shunt resistor)............................................................................................................ 9 6.4.1 differential input amplifier for current channel ........................................................................ ................................................. 10 6.4.2 differential input amplifier for voltage channel........................................................................ ................................................. 11 6.4.3 sigma delta analog to digital converter ................................................................................. .................................................. 12 6.4.4 bandgap reference voltage............................................................................................... ....................................................... 12 6.4.5 internal (programmable) current source fo r external temperature m easurement ............................................. ..................... 13 6.4.6 cmref circuit (vcm) ..................................................................................................... .......................................................... 14 6.4.7 internal avdd power-on reset ............................................................................................ ..................................................... 14 6.4.8 internal dvdd power-on reset............................................................................................ ..................................................... 14 6.4.9 low speed oscillator.................................................................................................... ............................................................. 14 6.4.10 high speed oscillator .................................................................................................. ............................................................ 15 6.4.11 external clock......................................................................................................... ................................................................. 15 6.4.12 internal temperature sensor............................................................................................ ....................................................... 15 6.5 system specifications ..................................................................................................... ................................................................... 16 7 detailed description........................................................................................................ ........................................................ 17 7.1 current measurement channel ............................................................................................... ........................................................... 17 7.2 voltage/temperature measurement channel ................................................................................... .................................................. 17 7.3 digital implementation of measurement path................................................................................ ..................................................... 18 7.4 modes of operation ........................................................................................................ .................................................................... 18 7.4.1 normal mode 1 (nom1) .................................................................................................... ........................................................ 19 7.4.2 normal mode 2 (nom2) .................................................................................................... ........................................................ 20 7.4.3 standby mode1 (sbm1) .................................................................................................... ........................................................ 21 7.4.4 standby mode2 (sbm2) .................................................................................................... ........................................................ 21 7.5 reference-voltage......................................................................................................... ..................................................................... 22 7.6 oscillators............................................................................................................... ............................................................................ 22 7.7 power-on reset ............................................................................................................ ..................................................................... 22 7.8 4-wire serial port interface .............................................................................................. .................................................................. 22 7.8.1 spi frame............................................................................................................... ................................................................... 23 7.8.2 write command........................................................................................................... .............................................................. 23 7.8.3 read command............................................................................................................ ............................................................. 24 7.8.4 timing .................................................................................................................. ...................................................................... 25 7.8.5 spi interface timing .................................................................................................... .............................................................. 26
www.austriamicrosystems.com/AS8510 revision 3.4 3 - 46 AS8510 datasheet - contents 7.9 control register.......................................................................................................... ........................................................................ 27 7.9.1 standby mode - power consumption ........................................................................................ ................................................ 38 7.9.2 initialization sequence at power on ..................................................................................... .................................................... 38 7.9.3 soft-reset using bit d[7] of reset register 0x09........................................................................ ............................................... 39 7.9.4 reconfiguring gain setting of pga ...................................................................................... .................................................... 40 7.9.5 configuring the device during normal mode ............................................................................... ............................................. 40 7.10 low side current measurement application ................................................................................. ................................................... 41 8 package drawings and markings ............................................................................................... ............................................ 42 8.1 recommended pcb footprint................................................................................................. ........................................................... 43 9 ordering information........................................................................................................ ....................................................... 45
www.austriamicrosystems.com/AS8510 revision 3.4 4 - 46 AS8510 datasheet - pin assignments 4 pin assignments figure 2. pin assignments (top view) 4.1 pin descriptions table 1. pin descriptions pin number pin name pin type description 1rshh analog input positive differential input for current channel 2rshl negative differential input for current channel 3ref analog output internal reference voltage to sigma-delta adc; connect 100nf to avss from this pin. 4vcm common mode voltage to the internal measurement path; connect 100nf to a vss from this pin. 5avdd supply pad +3.3v analog power-supply 6 avss 0v power-supply analog 7etr analog input voltage channel single ended input 8ets 9 vbat_in battery voltage (high) input 10 vbat_gnd battery voltage (low) input 11 cs digital input with pull-up chip select with an internal pull-up resistor (spi interface) 12 sclk digital input clock signal (spi interface) 13 sdo digital output serial data input (spi interface) vbat_in dvdd sdo sdi sclk cs avdd int clk dvss rshh rshl etr vcm ets chop_clk men avss ref AS8510 vbat_gnd 6 8 3 9 10 1 2 7 5 4 12 16 20 19 14 17 13 15 18 11
www.austriamicrosystems.com/AS8510 revision 3.4 5 - 46 AS8510 datasheet - pin assignments 14 dvss supply pad 0v digital ground 15 dvdd +3.3v digital supply 16 chop_clk digital output chop clock used in high side measurements to synchronize external chopper. (as an example, when as8525 is used to condition the input signal to the input range of AS8510, the chop clock is used by as8525.) 17 men digital output issued during the standby mode (sbm) to signal the short duration of data sampling. this signal is useful in the case of a high side measurement application. (for example: this signal is used by as8525 device to wake-up and enable the measurement path.) 18 sdi digital input data signal (spi interface) 19 clk digital i/o by default this pin is the internal clock output which can be used by a microcontroller. the internal clock may also be disabled as an output by programming register 08. to use an external clock, register 08 has to be programmed. 20 int digital output active high interrupt to indicate data is ready table 1. pin descriptions pin number pin name pin type description
www.austriamicrosystems.com/AS8510 revision 3.4 6 - 46 AS8510 datasheet - absolute maximum ratings 5 absolute maximum ratings stresses beyond those listed in table 2 may cause permanent damage to the device. these are stress ratings only. functional operation of the device at these or any other conditions beyond those indicated in electrical characteristics on page 7 is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 2. absolute maximum ratings parameter min max units notes electrical parameters dc supply voltage (avdd and dvdd) -0.3 5 v input voltage (v in )-0.3 avdd + 0.3 dvdd + 0.3 v input current (latchup immunity) (i scr ) -100 100 ma aec - q100 - 004 electrostatic discharge electrostatic discharge (esd) all pins 2 kv aec - q100 - 002 continuous power dissipation total power dissipation (all supplies and outputs) (p t ) 50 mw ssop20 in still air, soldered on jedec standard board @ 125o ambient, static operation with no time limit temperature ranges and storage conditions storage temperature (t strg ) -50 125 oc junction temperature (t j )130oc thermal resistance (r thjc ) 80 k/w jedec standard test board, 0 air velocity package body temperature (t body ) 260 oc norm: ipc/jedec j-std-020 the reflow peak soldering temperature (body temperature) is specified according ipc/ jedec j-std-020 ?moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices?. the lead finish for pb-free leaded packages is matte tin (100% sn). humidity non-condensing 5 85 %
www.austriamicrosystems.com/AS8510 revision 3.4 7 - 46 AS8510 datasheet - electrical characteristics 6 electrical characteristics 6.1 operating conditions 6.2 dc/ac characteristics for digital inputs and outputs all pull-up and pull-down have been implemented with active devices. sdo has been measured with 10pf load. table 3. operating conditions symbol parameter conditions min max units avdd positive analog supply voltage 3.0 3.6 v avss 0v ground 0 0 v a - d difference in analog and digital supplies 0.1 v dvdd positive digital supply 2.97 3.63 v dvss 0v digital ground 0 0 v t amb ambient temperature -40 125 oc i supp supply current 5.5 ma f clk system clock frequency 1 1. nominal clock frequency from external or internal oscillator. 4.096 mhz table 4. int symbol parameter conditions min typ max units i leak tri-state leakage current -1 +1 a v oh high level output voltage 2.5 v v ol low level output voltage 0.4 v i o output current 4 ma table 5. cs input symbol parameter conditions min typ max units v ih high level input voltage 2.0 v v il low level input voltage 0.8 v i leak input leakage current -1 +1 a ipu pull up current cs pulled to dv dd = 3.3v -150 -15 a table 6. sdi symbol parameter conditions min typ max units v ih high level input voltage 2.0 v v il low level input voltage 0.8 v i leak input leakage current -1 +1 a
www.austriamicrosystems.com/AS8510 revision 3.4 8 - 46 AS8510 datasheet - electrical characteristics table 7. sdo output symbol parameter conditions min typ max units v oh high level output voltage isource = 8ma 2.5 v v ol low level output voltage isink = 8ma 0.4 v i o output current 8 ma table 8. chop_clk output symbol parameter conditions min typ max units v oh high level output voltage 2.5 v v ol low level output voltage 0.4 v i o output current 4 ma table 9. clk i/o with input schmitt trigger and output buffer symbol parameter conditions min typ max units v ih high level input voltage dv dd = 3.3v 2.4 v v il low level input voltage dv dd = 3.3v 1.0 v i leak input leakage current -1 +1 a i pd pull down current clk pulled to dvss 10 100 a i o output current 4 ma v oh high level output voltage 2.5 v v ol low level output voltage 0.4 v table 10. sclk with input schmitt trigger symbol parameter conditions min typ max units v ih high level input voltage dv dd = 3.3v 2.4 v v il low level input voltage dv dd = 3.3v 1.0 v i leak input leakage current -1 +1 a table 11. men output symbol parameter conditions min typ max units v oh high level output voltage 2.5 v v ol low level output voltage 0.4 v i o output current 2 ma
www.austriamicrosystems.com/AS8510 revision 3.4 9 - 46 AS8510 datasheet - electrical characteristics 6.3 detailed system and block specifications 6.3.1 electrical system specifications 6.4 current measurement ranges (across 100 shunt resistor) note: the data rate at the output can be calculated according to the formula: fsout=2*fchop /r2 (r2 is down sampling ratio taki ng values 1, 2, 4 up to 32768 as powers of 2) table 12. electrical system specifications symbol parameter min typ max units notes idd nom current consumption normal mode 3 5.5 ma idd sbm current consumption standby mode 40 a average of normal mode power consumption over a period of 10sec when the device is in standby mode table 13. current measurement ranges symbol parameter imax [a] vsh [mv] pga gain nominal data rate (f out ) v inadc 1 [mv] 1. v inadc = vsh * gain, gain deviations to be considered according to table 15 and table 16 . psr 2 [db] 2. avdd, dvdd of 3.3v with 5% variation. i10 input current range of 10a in nom 10 1 100 @ 1 khz 100 60 i200 input current range of 200a in nom 200 20 40 @ 1 khz 800 60 i400 input current range of 400a in nom 400 40 25 @ 1 khz 1000 60 i1500 input current range of 1500a in nom 1500 150 5 @ 1 khz 750 60 i1 input current range of 1a in sbm 3 3. for low power current monitoring, single shot measurement is performed with internal oscillator. 1 0.1 100 @ 1 hz 10 60 i10 input current range of 10a in sbm 3 10 1 100 @ 1 hz 100 60 i200 input current range of 200a in sbm 3 200 20 40 @ 1 hz 800 60 table 14. valid combinations of the chopper clock, oversampling clock and decimation ratios over sampling frequency chopper frequency decimation ratio 1mhz 2khz 64 2mhz 2khz 64 2mhz 2khz 128 2mhz 4khz 64
www.austriamicrosystems.com/AS8510 revision 3.4 10 - 46 AS8510 datasheet - electrical characteristics 6.4.1 differential input am plifier for current channel notes: 1. leakage test accuracy is limited by tester resource accuracy and tester hardware. 2. for gain 100 pga input common mode is 0v and the minimum supply is 3.15v. 3. the measurement ranges are referred only by the gain of input amplifier, while other parameters such as bandwidth etc. are pro- grammed independently. 4. this parameter is not measured directly in production. it is measured indirectly via gain measurements of the whole path. i t is guaran- teed by design. 5. pole frequency of input amplifier changes with gain. the number is valid for the gain at g1, while the bandwidth will be hi gher for other ranges. this parameter is not measured in production. 6. based on device evaluation. not tested. 7. these offsets are cancelled if chopping enabled (default). 8. noise density calculated by taking system bandwidth as 150hz. 9. refer to measurement ranges shown in table 13 . 10. no impact on the measurement path. if the chopping is enabled, both the offset and offset drift will be eliminated. 11. for negative input voltages up to -160mv below ground, inpu t leakage is typically -20na @ 65oc due to forward conductance of protection diode. table 15. differential input amplifier for current channel symbol parameter conditions min typ max units v in _amp input voltage range rshh and rshl -160 +160 mv i in _amp input current 1, 11 rshh and rshl@ +160mv input voltage at 125oc with pga -50 2 50 na icm absolute input voltage range 2 -160 +300 mv g = g1 gain1 3, 4, 9 i10 100 g = g2 gain2 3, 4, 9 i200 40 g = g3 gain3 3, 4, 9 i400 25 g = g4 gain4 3, 4, 9 i1500 5 e gain deviation i = 1, 2, 3, 4 0.9 * gi 1.1 * gi f p _amp pole frequency 4, 5 15 khz t1 gain drift with temperature 6 -20oc to +65oc gain 5, 25, referenced to room temperature 0.3 % v osdrift offset drift with temperature 7, 10 350 v vos input referred offset 7, 10 after trim, for temperature range -20 to +65oc 350 v vos_ch chopping enabled 0 lsb vndin noise density 4, 8 25 nv/ hz thd total harmonic distortion for 150 hz input signal 70 db
www.austriamicrosystems.com/AS8510 revision 3.4 11 - 46 AS8510 datasheet - electrical characteristics 6.4.2 differential input amplifier for voltage channel notes: 1. input for the voltage channel can be as high as 1220mv, in this high input case pga will be bypassed. 2. leakage test accuracy is limited by tester resource accuracy and tester hardware, especially at low temperatures due to con densing moisture. 3. for gain 100 pga input common mode is 0v and the minimum supply is 3.15v. 4. the measurement ranges are referred only by the gain of input amplifier, while other parameters such as bandwidth etc. are pro- grammed independently. 5. this parameter is not measured directly in production. it is measured indirectly via gain measurements of the whole path. i t is guaran- teed by design. 6. pole frequency of input amplifier changes with changing the gain. the number is valid for the gain at g1, while the bandwid th will be higher for other ranges. this parameter is not measured in production. 7. noise density calculated by taking system bandwidth as 150hz. 8. based on device evaluation. not tested. 9. no impact on the measurement path. if the chopping is enabled, both the offset and offset drift will be eliminated. 10. for negative input voltages up to -160mv below ground, inpu t leakage is typically -20na @ 65oc due to forward conductance of protection diode. table 16. differential input amplifier for voltage channel symbol parameter conditions min typ max units vin_ amp input voltage range 1, 10 -160 +160 mv iin_ amp input current 2, 10 vbat_in, etr, ets @ +160mv input voltage at 125oc with pga -50 2 50 na icm absolute input voltage range 3 -160 +300 mv g = g1 gain1 4, 5 100 g = g2 gain2 4, 5 40 g = g3 gain3 4, 5 25 g = g4 gain4 4, 5 5 e gain deviation i = 1, 2, 3, 4 0.9 * gi 1.1 * gi f p _amp pole frequency 5, 6 15 khz v ndin noise density 5, 7 25 nv/ hz thd total harmonic distortion for 150hz input signal 70 db t 1 gain drift with temperature 8 -20oc to +65oc gain 5, 25, referenced to room temperature 0.3 % v os input referred offset 9 after trim at +65oc 350 v vos_ch chopping enabled 0 lsb v osdrift offset drift with temperature 9 350 v
www.austriamicrosystems.com/AS8510 revision 3.4 12 - 46 AS8510 datasheet - electrical characteristics 6.4.3 sigma delta analog to digital converter notes: 1. production test at 800mv. maximum v in can be 1.22v with vref=1.225v. 2. programmable. it is defined with respect to the first decimator in the ? adc. 3. programmable: internal clock is 1024/2048 khz; external clock max is 8192 khz. 4. dependent on fovs, r1 and r2. the bandwidth is calculated according to the formula: bw=fovs/(2*r1*r2); the sampling frequency at the output of the a/d converter is 2*bw. 5. defined at maximum input signal, bw=500 hz (1hz to 500 hz), fovs=1024 khz, r1=64, fchop=2 khz and r2=2. 6. reference voltage might be forced from external. 6.4.4 bandgap reference voltage notes: 1. accuracy at 65oc. 2. no dc current is allowed from this pin. 3. this is a design parameter and not production tested. table 17. sigma delta analog to digital converter symbol parameter conditions min typ max units vref reference voltage 6 1.225 v v inadc input range 1 at vref = 1.22v 0 1.22 v r1 oversampling ratio/decimation ratio 2 64 128 128 fovs oversampling frequency 3 1024/ 2048 khz res number of bits 16 bits bw bandwidth 4 1 500 hz s/n signal to noise ratio 5 90 db table 18. bandgap reference voltage symbol parameter conditions min typ max units v ref trim reference voltage after trim 1, 2 trim at 65oc 1.225 v vref acc reference voltage initial accuracy 1, 2 at 65oc 3.5 mv vref drift reference voltage temperature drift temperature range -20 to 65 oc (see note 4) 0.4 % temperature range -40 to 125 oc +0.4/ -0.6 % psrr ref psr @ dc 80 db sut avdd start up time with supply ramp 3 5ms sut pd start up time from power down 3 1ms r ndvref output resistance of band gap 200 500 v ndvref bandgap reference thermal noise density 3 300 nv/ hz cl vref output capacitor (ceramic) 100 nf esr vref 0.02 1
www.austriamicrosystems.com/AS8510 revision 3.4 13 - 46 AS8510 datasheet - electrical characteristics 6.4.5 internal (programmable) current so urce for external temperature measurement notes: 1. current value can be programmed in steps of 8mamps from 0 to 256 ma with a process error of 30%. 2. temperature coefficient is not important since external temperature measurement is a 2 step measurement. the value specifie d is guaranteed by design and will not be tested in production. 3. maximum voltage on pin etr (reference) can be calculated by given formula, where g is the gain of pga (g=100). 4. maximum voltage on pin etr, if pga is bypassed. 5. maximum voltage on pin ets, if pga is bypassed. table 19. external temperature measurement symbol parameter conditions min typ max units i curon 5-bit current source enabled 1 5-bit programmable current source 0 270 320 a i curoff 5-bit current source disabled limited by leakage 10 na t k _ cs temperature coefficient of current source 2 1000 ppm / ok v maxetr voltage on pin etr 3 1000/g mv v maxetrmod max voltage on pin etr when pga is bypassed 4 1.22 v v maxets voltage on pin ets for resistor sensor 3 1000/g v v maxetsmod max. voltage on pin ets when pga is bypassed 5 1.22 v
www.austriamicrosystems.com/AS8510 revision 3.4 14 - 46 AS8510 datasheet - electrical characteristics 6.4.6 cmref circuit (vcm) 6.4.7 internal avdd power-on reset 6.4.8 internal dvdd power-on reset 6.4.9 low speed oscillator table 20. cmref circuit symbol parameter min typ max units v vcm output voltage 1.6 1.7 1.8 v c l load capacitance 100 nf table 21. internal avdd power-on reset symbol parameter min typ max units v porhia power on reset threshold 2.2 2.4 2.6 v t pora por time - the duration from power on till the time, internal power on reset signal goes high 1 1. por pulse is always longer than t pora whatever the slope of the supply. 1s i pora current consumption in por block 2 2. i pora can not be switched off. 1.5 a table 22. internal dvdd power-on reset symbol parameter min typ max units v porhid power on reset threshold 2.2 2.4 2.7 v v hyst hysteresis 1 1. v porlo = v porhi - v hyst where v porlo is the lower threshold of por. 0.20.250.4 v t pord por time - the duration from power on till the time, internal power on reset signal goes high 2 2. v porlo = v porhi - v hyst where v porlo is the lower threshold of por. 1s i pord current 3 3. i pord can not be switched off. 1.5 a table 23. low speed oscillator symbol parameter min typ max units f ls frequency 262.144 khz f ls _ acc accuracy 7 % i ls supply current 5 a
www.austriamicrosystems.com/AS8510 revision 3.4 15 - 46 AS8510 datasheet - electrical characteristics 6.4.10 high speed oscillator notes: 1. accuracy after trimming. 2. accuracy for limited temperature range of -20 to 65 oc. 6.4.11 external clock 6.4.12 internal temperature sensor table 24. high speed oscillator symbol parameter min typ max units f hs frequency 4.096 mhz f hsacc accuracy 1, 2 4 % i hs supply current 300 a table 25. external clock symbol parameter conditions min typ max units f clkext clock frequency 2048/ 4096/ 8192 khz div clkext clock division factor to be programmed in register 08 clk_reg through the serial bus spi. 2/4/8 dc clkext duty cycle of external clock 40 60 % table 26. internal temperature sensor symbol parameter conditions min typ max units t intrng temperature sensor range -40 125 oc tin temperature measurement accuracy 3 oc t intslp temperature sensor slope guaranteed by design; at pga gain 5 which is the recommended gain for internal temperature measurement. 27 digits/c t int 65 g 5 temperature sensor output at gain 5 40660 41807 43012 digits
www.austriamicrosystems.com/AS8510 revision 3.4 16 - 46 AS8510 datasheet - electrical characteristics 6.5 system specifications system measurement error budget for voltage and current channel. temperature range: -20oc to +65oc; output data rate is 1khz, v cc = 3.3v, chopping enabled. notes: 1. these specifications are defined by taking one channel as reference and measured on the other channel. 2. guaranteed by design. 3. system measurement error due to noise, individual block parameter drifts and non linearity. based on evaluation, not tested . 4. system error due to offset is neglected because of chopper architecture. table 27. system specifications symbol parameter min typ max units i s channel to channel isolation 1 -90 db at difference in channel to channel attenuation @600hz 1, 2 3db ph difference in phase shift between the two channels @600hz 1, 2 5deg table 28. system measurement error budget for gains 5 and 25 symbol parameter conditions min typ max units err system measurement error 3, 4 0.5 0.8 % measurement error due to pga gain drift from device evaluation 0.3 % measurement error due to v ref drift6 0.4 % measurement error due to non-linearity of pg tested by distortion measurements 0.025 %
www.austriamicrosystems.com/AS8510 revision 3.4 17 - 46 AS8510 datasheet - detailed description 7 detailed description the AS8510 consists of two independent high resolution 16-bit sd analog to digital conversion channels. the measurement path of these two channels integrates a programmable gain amplifier, chopper and de-chopper, sigma-delta modulator, decimator and a digital filte r for simultaneous measurement of current and voltage/temperature. the two measurement channels, namely the current and voltage/temperature measurement channels have identical data path. the input signal is amplified in the programmable gain amplifier (pga) with any of the selected gains of 1, 5, 25, 40 and 100 f acilitating measurement of a wide range of current, voltage and temperature levels. gain settings for different input ranges and any associ ated restrictions are explained in the table 13 . offset in the measurement path is minimized with the use of a chopper and a de-chopper at appropriate stages in the data path. by default the chopper/de-chopper is on in the measurement path. it ma y be disabled by programming the appropriate register. the amplified input signal is converted into a single-bit pulse-density modulated stream by the - modulator. a decimator acting as a low-pass filter filters out the quantization noise and generates 16-bit data corresponding to the input signal. the decimation ratios of 64, 128 may be selected in the first filter stage. for reducing data rate further, the second stage decimation can be used. an optional fir filter is provided to offer matched low pass filter response typically required in lead acid battery sensor sys tems. 7.1 current measurement channel the voltage across a shunt resistor, connected in series with the battery negative terminal, forms the input signal to the curr ent measurement channel. rshh and rshl are the current measurement input pins. offset in the input signal is nullified with the use of a choppe r and a de- chopper at appropriate stages in the data path. the programmable gain amplifier in the data path with programmable settings of 1, 5, 25, 40 and 100 enables measurement of current ranges from 1a to 1500a. the sampled input signal is converted into a single-bit pulse-den sity modulated stream by the - modulator. a decimator acting as a low-pass filter filters out the quantization noise and generates 16-bit data equivalent to the input current signal. the programmable input sampling rate and the decimation ratio determine the output data rates. the data path can be programmed to provide 1hz to 2 khz rates in the various modes available. an optional fir filter is provided to offe r matched low pass filter response typically required in lead acid battery sensor systems. after enabling the current measurement channel, the delay for the availability of the first sample is two conversion cycles. 7.2 voltage/temperature measurement channel the other two parameters of the battery for measurement are voltage and its temperature. the second channel accepts signals fro m four independent sources through a multiplexer as listed below: an attenuated battery voltage obtained through appropriate external resistor divider, (or) a signal from the external temperature sensor, (or) a signal from external reference, (or) a signal from the internal temperature sensor. apart from this difference in the multiplexing of four input signals, the rest of the data path is identical to the current mea surement channel. rshh and rshl are the current measurement input pins the battery voltage which can go up to 18v is attenuated through a resistor divider externally and is applied to the voltage ch annel. for automotive battery measurement, the gain of the pga should be restricted to 5 and 25. the latency for the first result from the voltage measurement channel is two conversion cycles. a second option on this measurement channel is to measure temperature. internally generated constant current is pumped through the temperature sensor with positive temperature coefficient, and, a high- precision resistor. the voltages across the sensor and t he resistor form the inputs to the measurement channel one at a time. the difference between the two voltages which is independent of the magnit ude of the current is used to determine the temperature accurately. the vo ltage across the sensor is applied between the ets and vss pins and, the voltage across the high-p recision resistor is appl ied between etr and vss. external temper ature measurement involves the acquis ition of two signals one after the other using the same constant current source. the latency for the first result from the temperature measu rement channel is two conversion cycles. a third option on the measurement channel is to measure the internal temperature. hence, one of the three options for measureme nt of battery voltage, external temperature and, internal temperature may be ca rried out by selection of appropriate inputs through the inter nal multiplexer selection.
www.austriamicrosystems.com/AS8510 revision 3.4 18 - 46 AS8510 datasheet - detailed description 7.3 digital implementati on of measurement path figure 3. block diagram of digital implementation figure 3 shows the digital implementation of the decimator and filter to process the 1-bit output of the modulator. this block receives a 1-bit pulse density modulated output (mod_in) from the second order sigma delta modulator along with the oversampling frequency clock (mod_ clk). the mod_clk directly goes to a clock division block, which genera tes chopper clock (chop_clk). the chop_clk can be one of 2khz or 4khz selected by register clk_reg in table 33 . the mod_clk can be either 1mhz or 2mhz. the decimation is a two phase process. in the first phase, the r1 down sampling rate can be obtained by select ing either 64 or 128 in regist ers decreg_r1_i, decreg_r1_v in table 33 . the 16-bit cic1 output is dechopped with respect to chop_clk. the output of dechopper is passed through the cic2 filter with a decimation ratio of 1to 32768 in steps of power of 2. this output is then processed through a fir or moving average (ma) filter. fir filte r is provided to offer matched low pass filter response typically required in lead acid battery sensor systems. ma filter is used to provide averaged output and the number of samples for averaging can be any integer value from 1 to 15. 7.4 modes of operation the device operates in four different modes, namely, normal mode 1 (nom1), normal mode 2 (nom2), standby mode 1 (sby1), and, standby mode 2 (sby2). the normal modes are full-power modes with the exception that in normal mode 2, sampling is normally at a programmed lower freq uency and is increased to a higher rate only when a measured input signal level crosses the programmed threshold in the current measureme nt channel. the standby modes are lower power modes. sampling is normally at a very low frequency interval. in standby mode 2, data samplin g can be carried out only when the internal comparator detects the input current to be greater than the programmed threshold and it gene rates interrupt on the int pin. the device enters into the ?stop? state on power on. this is a state where in the data path is inactive and can be entered into from any of the four modes. the state transition diagram involving the state of stop and the four modes is illustrated in the figure 4 . cic1 64 / 128 clk division block dechopper fir/ma mod_in mod_clk dataout r1 r1 = first decimation ratio (64 or 128) r2 = second decimation ratio (1 to 32768) mod_clk r1 cic2 r2 fir_ma_sel chp_clk f mod / r1 f chop * 2 f chop * 2 / r2 f chop f mod f chop * 2 / r2
www.austriamicrosystems.com/AS8510 revision 3.4 19 - 46 AS8510 datasheet - detailed description figure 4. state transition diagram 7.4.1 normal mode 1 (nom1) on power-on-reset of the device, AS8510 goes into stop state. transition to normal mode1 (nom1) occurs when the ?sta rt bit? d0 of mode control register mod_ctl_reg in table 33 is set to ?1? through the serial port spi. data rate of voltage and current channels can be independently programmed and both the channels ge nerate interrupts for every output available from adc. the interrupt signal is generated on the int pin. the width of the interrupt pu lse is eight cycles of lp_clk. the data is stable up to the next interrupt. if the data rate is different for the two channels, the interrupt rate wou ld follow the higher rate among the two channels. data update can be known by reading the status register. the functionality is explained in the waveform shown in figure 5 . when the device is configured to nom1 mode from any mode the configuration should be through the stop state only. stop otp_int reset norm a_stb por_avdd otp_load stop sbm_on sbm_off s t o p s t a r t s t o p norm or stop analog stablization period wait for 1.5msec 1.5msec & sbm 1.5msec & norm nor m sbm wait for tt1 timeout tt1 _ t i meout wait for x number of conversions wait for otp_load completes in 32 cycles of lp_clk !por_avdd sbm !por_dvdd
www.austriamicrosystems.com/AS8510 revision 3.4 20 - 46 AS8510 datasheet - detailed description figure 5. normal mode 1 7.4.2 normal mode 2 (nom2) nom2 differs from nom1 in such a way that it allows for a relaxed data rate at a period of t mc by programming the corresponding register as long as the amplitude of current is less than a programmed threshold i thc . however, when, the measured input signal exceeds the programmed threshold, the data rate is changed to the rate of nom1 mode. transition to nom2 occurs when the ?start bit? d0 of mode control register mod_ctl_reg in table 33 is set to 1 and mode control bits to 01 through spi. in this mode the data rate should be programmed with the time of t mc . an interrupt signal is generated on int at the rate of t mc secs with a pulse width of eight cycles of lp_clk. the data is stable up to the next interrupt. the data sample is compared aga inst the programmed threshold and when it is exceeded, the data sampling rate is changed to provide data at the data rate of nom1 mode. however, as soon as the data sample amplitude falls below the programmed threshold, the sampling rate is restored to provide data at the ra te of t mc . the functionality is illustrated in the waveform figure 6 . figure 6. normal mode 2 sampling with f1 int at f1 rate from current channel current channel data register t i start stop t v,t sampling with f2 voltage channel data register interrupt from the current channel is at f1 rate which is integer multiple of f2 rate from voltage channel i data v,t data t int i dd t t mc t mc sampling with f i ths i v,i,t v,i,t v,i,t i > i ths v,i,t v,i,t i < i ths int t int
www.austriamicrosystems.com/AS8510 revision 3.4 21 - 46 AS8510 datasheet - detailed description 7.4.3 standby mode1 (sbm1) the low-power standby mode can be entered only through the stop st ate. transition to sbm1 mode occurs when the ?start bit? d0 o f mode control register mod_ctl_reg in table 33 is set to ?1? and mode control bits to ?10? through spi. in this mode the date rate is programmable with the time of ta. an interrupt signal is generated on int at the rate of ta secs., and with a pulse width of eight cycles of lp_clk. the data is stable up to the next interrupt. the functionality is illustrated in figure. during the period of ta, only one data sample is m ade available and, during the rest of the period, the device is maintained in stop state to reduce power consumption. the microcontroller which re ceives the data on the interrupt, is also expected to be processing the data for a short time as shown clearly in the figure 7 to ensure the overall low-power consumption of the data acquisition and processing system. figure 7. standby mode 1 7.4.4 standby mode2 (sbm2) standby mode 2 is an extension of the standby mode1 to achieve even a lower power in the data acquisition system by providing i nterrupt to the microcontroller only when the data sample exceeds the set current threshold. the standby mode can be entered only through the s top state. transition to sbm2 mode occurs when the ?start bit? d0 of mode control register mod_ctl_reg in table 33 is set to ?1? and mode control bits d7,d6 to ?1,1? through spi. in this mode the date rate is pr ogrammable with the time of ta in the ta control registers b, c. the data sample is made available and an interrupt signal is generated on int pin only when the input signal exceeds the threshold set in curre nt threshold registers d,e. it should be noted here that the data is stable for ta secs. the functionality is illustrated in figure 8 . figure 8. standby mode 2 mcu adc t t start sbm1 t a sec. t a sec. t a sec. i dd v, i, t t t v, i, t mcu conv conv conv mcu int channel data register data ? a1 data ? a0 data ? a2 data ? a3 t int adc t t conv start sbm2 t a sec. t a sec. t a sec. i dd i t conv t conv i mcu |i| > i threshold int channel data register data ? a1 data ? a0 data ? a2 data ? a3 t int
www.austriamicrosystems.com/AS8510 revision 3.4 22 - 46 AS8510 datasheet - detailed description 7.5 reference-voltage band gap-reference voltage is used for the adc as a reference and for the generation of the current for external temperature me asurement. 7.6 oscillators a high-speed oscillator (hs) generates the oversampling clock. for internal state machine and interrupt generation, a low-speed oscillator (ls) is also available. 7.7 power-on reset the AS8510 has pors, apor and dpor on analog and digital power supplies respectively. on pors of both supplies, initialization sequence happens and the system status is shown in state diagram (see figure 4) . as shown in the state diagram, the system is in reset state until dpor output goes to logic high and subs equently until apor ou tput goes to logic high. once analog power supply is available, the system goes into otp_int state and loads the default values into the con trol and data registers and goes into stop stat e. if analog por, apor goes low at any time, the system goes into reset state. in the stop sta te, the AS8510 can be programmed and by giving start command it starts working following the state machine. 7.8 4-wire serial port interface the spi interface is used as interface between the AS8510 and an external micro-controller to configure the device and access t he status information. the micro-controller begins communication with the spi which is configured as a slave. the spi protocol is simple and the length of each frame is an integer multiple of bytes except when a transmission is started. each frame has 1 command bit, 7 address/confi guration bits, and one or more data bytes. the edge of cs and the level of sclk during the start of a spi transaction, determine the edge on w hich the data is transferred from the spi and the edge on which the data is sampled by the slave. table 29 describes the setting of the transfer and sampling edges of sclk. figure 9 shows the falling edge and rising edge for data transfer and data sampling respectively, when sclk is high on the falling edge of cs. figure 9. protocol for serial data write with length = 1 table 29. cs and sclk cs sclk description fall low serial data transferred on rising edge of spi clock. sampled at falling edge of spi clock. fall high serial data transferred on falling edge of spi clock. sampled at rising edge of spi clock. any any serial data transfer edge is unchanged. cs sclk sdi sdo 0 a6 a5 a4 a0 a1 a2 a3 d0 d1 d2 d3 d4 d5 d7 d6 transfer edge sampling edge data d7 ? d0 is moved to address a4..a0 here
www.austriamicrosystems.com/AS8510 revision 3.4 23 - 46 AS8510 datasheet - detailed description 7.8.1 spi frame a frame is formed by a first byte for command and address/configuration and a following bit stream that can be formed by an int eger number of bytes. command is coded on the 1 first bit, while address is given on lsb 7 bits (see table 30) . if the command is read or write, one or more bytes follow. wh en the micro-controller sends more bytes (keeping cs low and sclk toggling), the spi interface increments the address of the previous data byte and writes/reads data to/from consecutive addresses. 7.8.2 write command for write command, c0=0. after the command code c0 is transferred, the address of register to be written is provided from msb t o lsb. subsequently one or more data bytes can be transferred from msb to lsb. for each data byte following the first one, used addres s is the incremented value of the previously written address. each bit of the frame has to be driven by the spi master on the spi clock transfer edge. the spi slave samples it on the next clock edge. these edges are determined by the level of sclk as shown in table 29 . figure 10 and figure 11 are examples of write command without and with address self-increment. figure 10. protocol for serial data write with length = 1 table 30. command bits command bits register address or transmission configuration c0 a6 a5 a4 a3 a2 a1 a0 table 31. command bits c0 command description 0 write address writes data byte on the given starting address. 1 read address read data byte from the given starting address. cs sclk sdi sdo 0 a6 a5 a4 a0 a1 a2 a3 d0 d1 d2 d3 d4 d5 d7 d6 data d7 ? d0 is moved to address a4..a0 here
www.austriamicrosystems.com/AS8510 revision 3.4 24 - 46 AS8510 datasheet - detailed description figure 11. protocol for serial data write with length = 4 7.8.3 read command for read command c0=1. after the command code c0, the address of register to be read is provided from msb to lsb. then one or m ore data bytes can be transferred from the spi slave to the master, always from msb to lsb. to transfer more bytes from consecutive addr esses, spi master keeps cs signal low and spi clock active as long as it desires to read data from the slave. each bit of the command and address of the frame is to be driven by the spi master on the spi clock transfer edge where spi slave samples it on the next spi clock edge. each bit of the data section of the frame is driven by the spi slave on the spi clock transfer edge and spi master samples it o n the next spi clock edge. these edges are determined as per table 29 and examples of read command without and with address self-increment. figure 12. protocol for serial data read with length = 1 cs sclk sdi sdo 0 a 6 a 1 a 4 a 2 a 3 d 0 d 1 d 2 d 3 d 4 d 5 d 7 d 6 data d7-d0 is moved to address a4-a0 here data d7-d0 is moved to address a4-a0 +1 here data d7-d0 is moved to address a4-a0 +2 here data d7-d0 is moved to address a4-a0 +3 here data d7-d0 is moved to address a4-a0 +4 here a 0 a 5 d 1 d 2 d 3 d 4 d 5 d 7 d 6 d 0 d 1 d 2 d 3 d 4 d 5 d 7 d 6 d 0 d 1 d 2 d 3 d 4 d 5 d 7 d 6 d 0 d 1 d 2 d 3 d 4 d 5 d 7 d 6 d 0 cs sclk sdi sdo 1 a6 a5 a4 a0 a1 a2 a3 d0 d1 d2 d3 d4 d5 d7 d6 data d7 ? d0 at address a4..a0 is read here
www.austriamicrosystems.com/AS8510 revision 3.4 25 - 46 AS8510 datasheet - detailed description figure 13. protocol for serial data read with length = 4 7.8.4 timing in the following timing waveforms and parameters are exposed. figure 14. write timing for writing cs sclk sdi sdo 1 a 6 a 5 a 4 a 0 a 1 a 2 a 3 d 0 d 1 d 2 d 3 d 4 d 5 d 7 d 6 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 data d7-d0 at address a4-a0 is read here data d7-d0 at address a4-a0 +1 is read here data d7-d0 at address a4-a0 +2 is read here data d7-d0 at address a4-a0 +3 is read here data d7-d0 at address a4-a0 +4 is read here cs sdi sdo sclk ... ... ... t cps t cphd t dis t dih clk polarity datai datai datai ... t csh t sclkh t sclkl
www.austriamicrosystems.com/AS8510 revision 3.4 26 - 46 AS8510 datasheet - detailed description figure 15. read timing for reading 7.8.5 spi interface timing table 32. spi interface timing symbol parameter conditions min typ max units general br spi bit rate 1 mbps t sclkh clock high time 400 ns t sclkl clock low time 400 ns write timing t dis data in setup time 20 ns t dih data in hold time 20 ns t csh cs hold time 20 ns read timing t dod data out delay 80 ns t dohz data out to high impedance delay time for the spi to release the sdo bus 80 ns timing parameters when entering 4-wire spi mode (for determination of clk polarity) t cps clock setup time (clk polarity) setup time of sclk with respect to cs falling edge 20 ns t cphd clock hold time (clk polarity) hold time of sclk with respect to cs falling edge 20 ns cs sclk sdi sdo t dohz t dod datai datai datao (d7 ) datao (d0 ) t sclkh t sclkl
www.austriamicrosystems.com/AS8510 revision 3.4 27 - 46 AS8510 datasheet - detailed description 7.9 control register this section describes the control registers used in AS8510. registers can be broadly classified into the following categories. data access registers status registers digital signal path control registers digital control registers analog control registers table 33. control registers addr in hex register name por value r/w 8-bit control / status data data access registers 00 dreg_i1 (adc data register for current) 0000_0000 r d[7:0] denotes the current adc msb byte (adc_i[15:8]) 01 dreg_i2 (adc data register for current) 0000_0000 r d[7:0] denotes the current adc lsb byte (adc_i[7:0]) 02 dreg_v1 (adc data register for voltage) 0000_0000 r d[7:0] denotes the voltage adc msb byte (adc_v[15:8]) 03 dreg_v2 (adc data register for voltage) 0000_0000 r d[7:0] denotes the voltage adc lsb byte (adc_v[7:0]) status registers 04 status_reg 0000_0000 r d[7] nom1/nom2 data ready d[6] nom2 threshold crossover d[5] sbm1 data ready d[4] sbm2 threshold crossover d[3] apor status d[2] data from current channel updated d[1] data from voltage channel updated d[0] reserved
www.austriamicrosystems.com/AS8510 revision 3.4 28 - 46 AS8510 datasheet - detailed description digital signal path control registers for current channel 05 dec_reg_r1_i 0100_ 0101 r/w d[7] this bit selects decimation rate is used for current channel. default is 0 (down sampling rate is 64) 0 down sampling rate is 64 1 down sampling rate is 128 d[6:5] these two bits select division ratio of oversampling frequency clock mod_clk to be used as chopper clock, chop_clk. default is ?10? (divide by 512) 00 chopper clock always high 01 divide by 256 10 divide by 512 11 divide by 1024 d[4:1] these four bits select the decimation ratio of second cic stage. default is ?0010? (equal to 4) 0000 1 0001 2 0010 4 0011 8 0100 16 0101 32 0110 64 0111 128 1000 256 1001 512 1010 1024 1011 2048 1100 4096 1101 8192 1110 16384 1111 32768 d[0] cic1 saturation interrupt mask control. default is 1 0unmask 1mask table 33. control registers addr in hex register name por value r/w 8-bit control / status data
www.austriamicrosystems.com/AS8510 revision 3.4 29 - 46 AS8510 datasheet - detailed description 06 dec_reg_r2_i 1100_0101 r/w d[7] i-channel enable, default 1=enable d[6] v-channel enable, default 1=enable d[5] interrupt polarity 0 active high 1 active low d[4] . interrupt mask control for current channel data ready interrupt on int pin (default is 0) 0unmasked 1masked d[3:2] these two bits select the source of output 16-bit data in normal mode from current channel. default is 01 00 fir / ma output 01 cic2 output 10 dechop/demod output 11 cic1 output d[1:0] these two bits select the source of output 16-bit data in sbm mode from current channel. default is 01 00 fir / ma output 01 cic2 output 10 dechop/demod output 11 cic1 output table 33. control registers addr in hex register name por value r/w 8-bit control / status data
www.austriamicrosystems.com/AS8510 revision 3.4 30 - 46 AS8510 datasheet - detailed description 07 fir ctl_reg_i 0000_0100 r/w d[7] this bit selects fir / ma filter in current channel. default is 0 (fir) 0fir 1ma filter d[6:3] these bits select the number of data samples for averaging in ma filter in current channel. default is 0000 (bypass) 0000 bypass 0001 1 0011 3 0111 7 1111 15 d[2:1] these two bits select the measurement path architecture in both current and voltage channels. default is 10 (dechopper after cic) 00 demodulator after cic1 01 demodulator before cic1 10 dechopper after cic1 (preferred and suggested) 11 demodulator before cic1 with settled sample d[0] reserved. default 0. do not change table 33. control registers addr in hex register name por value r/w 8-bit control / status data
www.austriamicrosystems.com/AS8510 revision 3.4 31 - 46 AS8510 datasheet - detailed description digital control registers 08 clk_reg (clock control register) 0010_0000 r/w d[7:6] oversampling frequency clock selection. default is 00 (high speed (hs) internal clock) 00 internal hs clock with no clock output 01 internal hs clock with clock output 10 external clock d[5:4] these two bits select the division ratio for hs clock/ external clock. default is 10 (division by 4) 00 no division 01 divide by 2 10 divide by 4 11 divide by 8 d[3:2] these two bits select the division ratio of hs clock, by which it should be divided before providing it on clk pin. default is 00 (no division) 00 no division 01 divide by 2 10 divide by 4 11 divide by 8 d[1] this bit selects the division ratio of ls clock 0 ls _clk undivided (low speed clock) 1 ls _clk divide by 2 d[0] reserved 09 reset_reg (reset control register) 1100_0000 r/w d[7] entire device can be soft reset by writing ?0? into this register bit. this bit will take a default 1 value on coming out of reset d[6] measurement path can be soft reset by writing ?0? into this register bit. this bit will take a default 1 value after measurement path is reset. d[5:0] reserved table 33. control registers addr in hex register name por value r/w 8-bit control / status data
www.austriamicrosystems.com/AS8510 revision 3.4 32 - 46 AS8510 datasheet - detailed description 0a mod_ctl_reg (mode control registers) 0000_0000 r/w d[7:6] these two bits select the operating mode of the device. default is 00 (normal mode 1) 00 normal mode 1 01 normal mode 2 10 standby mode 1 11 standby mode 2 d[5:3] these three bits select the number of cycles to be ignored before comparison with the set threshold in standy mode. default is 000 (3 cycles of data) 000 3 cycles of data 001 4 cycles of data 010 5 cycles of data 011 6cycles of data 100 7 cycles of data 101 8 cycles of data 110 9 cycles of data 111 10 cycles of data d[2] this bit controls the chop_clk availability on chop_clk pin. default is 0 0 disabled 1 enabled d[1] enabling the men pin to indicate transition from standy to normal mode. 0 disabled 1 enabled d[0] this bit is used to take the device from stop state to any of the modes based on d[7:6] selection of this register. 0 retain in stop state 1 enables transition to normal or standby modes. 0b mod_ta_reg1 (ta control register) 1000_0000 d[7] unit of ta in sbm1/sbm2. default is 1 0 unit is in milliseconds 1 unit is in seconds d[6:0] msb value of ta 0c mod_ta_reg2 (ta control register) 0000_0000 r/w d[7:0] unit of ta in sbm1/sbm2 lsb value of ta 0d mod_i th _reg1 (current threshold register) 0000_0000 r/w d[7:0] msb bits of 16 bits sbm2 threshold register 0e mod_i th _reg2 (current threshold register) 0000_0000 r/w d[7:0] lsb bits of 16 bits sbm2 threshold register table 33. control registers addr in hex register name por value r/w 8-bit control / status data
www.austriamicrosystems.com/AS8510 revision 3.4 33 - 46 AS8510 datasheet - detailed description 0f mod_t mc _reg1 (t mc control registers) 0000_0000 r/w d[7:0] msb value of number of data samples to be dropped from adc before sending interrupt in nom2 10 mod_t mc _reg2 (t mc control register) 0000_0000 r/w d[7:0] lsb value of number of data samples to be dropped from adc before sending interrupt in nom2 11 nom_i th _reg1 0000_0000 r/w d[7:0] eight msb bits of nom2 current threshold register 12 nom_i th _reg2 0000_0000 r/w d[7:0] eight lsb bits of nom2 current threshold register analog control registers 13 pga_ctl_reg (pga control registers) 0101_0000 r/w d[7:6] setting of gain g of current channel pga. default is 01 (g = 25) 00 5 01 25 10 40 11 100 d[5:4] setting of gain g in voltage channel. default is 01 (g = 25) 00 5 01 25 10 40 11 100 d[3:0] reserved 14 pd_ctl_reg_1 (power down control register) 1100_1111 r/w d[7] 0 disable chopper clock to current channel 1 enable chopper clock to current channel d[6] 0 disable chopper clock to voltage channel 1 enable chopper clock to voltage channel d[5] reserved d[4] reserved d[3] 0 disable current channel pga 1 enable current channel pga d[2] 0 disable current channel ? modulator 1 enable current channel ? modulator d[1] 0 disable voltage channel pga 1 enable voltage channel pga d[0] 0 disable voltage channel ? modulator 1 enable voltage channel ? modulator table 33. control registers addr in hex register name por value r/w 8-bit control / status data
www.austriamicrosystems.com/AS8510 revision 3.4 34 - 46 AS8510 datasheet - detailed description 15 pd_ctl_reg_2 (power down control register) 1111_0011 r/w d[7] 0 disable cic1 of both channels 1 enable cic1 of both channels d[6] 0 disable cic2 of both channels 1 enable cic2 of both channels d[5] 0 disable dechopper in both channels 1 enable dechopper in both channels d[4] 0 disable fir in both channels 1 enable fir in both channels d[3] 0 do not bypass pga in current channel default 0 1 bypass pga in current channel d[2] 0 do not bypass pga in voltage channel default 0 1 bypass pga in voltage channel d[1] 0 disable current channel chopper 1 enable current channel chopper d[0] 0 disable voltage channel chopper 1 enable voltage channel chopper 16 pd_ctl_reg_3 (power down control register) 1111_1000 d[7] 0 disable common mode reference 1 enable common mode reference d[6] 0 disable internal current source 1 enable internal current source d[5] 0 disable internal temperature sensor 1 enable internal temperature sensor d[4] reserved. (default 1) do not change d[3] reserved. (default 1) do not change d[2] 0 data output in binary numbering system 1 data output in 2?s complement numbering system d[1] reserved. (default 0) do not change d[0] reserved table 33. control registers addr in hex register name por value r/w 8-bit control / status data
www.austriamicrosystems.com/AS8510 revision 3.4 35 - 46 AS8510 datasheet - detailed description 17 ach_ctl_reg (analog channel selection register) 0000_0000 r/w d[7:6] these bits specify the selection of voltage/temperature in voltage channel default is 00 (voltage channel) 00 voltage channel 01 external temperature channel etr 10 external temperature channel ets 11 internal temperature channel d[5] reserved. (default 0) do not change d[4] internal current source switch enable. default is 0 note: d4 bit is used for enabling current source to the channel selected by bits d[7,6] of this register. 0 disabled 1 enabled d[3] enable/disable internal current source to rshh pin of current channel 0 disabled 1 enabled d[2] enable/disable current source switch to rshl pin of current channel 0 disabled 1 enabled d[1:0] reserved 18 isc_ctl_reg (current source setting register) 0000_0000 r/w d[7:3] these three bits specify the selection of magnitude of current from the internal current source. default is 00000 (0a). 00000 0a 00001 8.5a 00010 17a 00100 34.5a 01000 68a 10000 135a 11111 270a d[2:0] reserved 19 otp_en_reg 0000_0000 r/w d[7] 1 reserved (default = 1) do not change d[6:0] reserved 44 status_reg_2 0000_0000 r d[7] status indicating data saturation in current channel d[6] status indicating data saturation in voltage channel d[5:0] reserved table 33. control registers addr in hex register name por value r/w 8-bit control / status data
www.austriamicrosystems.com/AS8510 revision 3.4 36 - 46 AS8510 datasheet - detailed description digital signal path control registers for voltage channel 45 dec_reg_r1_v 0100_ 0101 r/w d[7] selection of decimation ratio for voltage/temperature channel. default is 0 (down sampling rate is 64) 0 down sampling rate is 64 1 down sampling rate is 128 d[6:5] division of oversampling clock, which is used as chopper clock. default is 10 (divide by 512) 00 chopper clock always high 01 divide by 256 10 divide by 512 11 divide by 1024 d[4:1] decimation ratio of cic2. default is 0010 (4) 0000 1 0001 2 0010 4 0011 8 0100 16 0101 32 0110 64 0111 128 1000 256 1001 512 1010 1024 1011 2048 1100 4096 1101 8192 1110 16384 1111 32768 d[0] cic1 saturation interrupt mask control. default is 1 0unmasked 1masked table 33. control registers addr in hex register name por value r/w 8-bit control / status data
www.austriamicrosystems.com/AS8510 revision 3.4 37 - 46 AS8510 datasheet - detailed description note: all the registers from address 0x19 to 0x2c are read-only. 7.9.1 standby mode - power consumption in standby mode 1 there is a timer based accurate measurement every ta seconds. the device itself stays in idle-mode as long as it does not get a different command from the spi interface. internal oscillator frequency is typically foscint=262 khz to reduce power cons umption as long as the timer runs. after every time out of ta secs, it performs accurate measurement of current, voltage/ temperature. data ready is signaled to microcontroller through an interrupt signal on int and goes into stop state. in the sbm the following equations hold: t sbm1 = ta= 10s (default value is 10secs); the power consumption is valid for this setting. this is the period of the repetition rate in sbm 1 and sbm2. t sett 2ms (depending on external capacitors). this is the time required by the analog part to settle when the new measuring period i s started. any measurements performed during t sett produce invalid results. t1 = 3ms (by default setting, every third measurement is sent to microcontroller in the sbm mode 1) is the time needed to perfo rm the first measurement. t meas =t sett +t1 is the total active time needed to get a valid result. dr sbm = t meas /t sbm 5ms/10s. this is the ratio of repetition time versus the active time (device in nom mode). power consumption = (dr sbm *nom mode power consumption) + ((10s-5ms)/10s)*stop mode power consumption) 46 dec_reg_r2_v 0000_0100 r/w d[7:5] reserved d[4] interrupt mask control for voltage channel data ready interrupt on int pin (default is 0) 0unmasked 1masked d[3:2] these two bits select the source of output 16-bit data in normal mode from voltage channel. default is 01 00 fir / ma output 01 cic2 output 10 dechop/demod output 11 cic output d[1:0] reserved 47 fir ctl_reg_v 0000_0000 r/w d[7] this bit selects fir / ma filter in voltage channel. default is 0 (fir) 0fir 1ma filter d[6:3] these bits select the number of data samples for averaging in ma filter in voltage channel. default is 0000 (bypass) 0000 bypass 0001 1 0011 3 0111 7 1111 15 d[2:0] reserved table 33. control registers addr in hex register name por value r/w 8-bit control / status data
www.austriamicrosystems.com/AS8510 revision 3.4 38 - 46 AS8510 datasheet - detailed description 7.9.2 initialization sequence at power on figure 16. AS8510 device initialization sequence at power on device initialization starts if the dvdd and avdd supplies are switched on and dvdd > v porhid . the duration period of initialization is 500sec, and, during this period, int pin toggles at the rate of internal low power oscillator. toggling on int during the peri od of initialization should be ignored in the system. device configuration and activation should be carried out only after the initialization period . on adc start, device enters into analog stabilization state and takes 1.5msec for oscillator and reference to settle. after thi s 1.5msec period, the first interrupt will occur after a time period of t adc . t data _ status _ rd is the time period during which the micro-controller should complete reading of data and status from the device. if reading is carried out beyond this time period, then, adc performance will degrade for next sample generation. status register gets cleare d automatically only when micro-controller reads this register. data in the channel registers is changed after t data _ valid duration. ensure that data channel registers and status registers are not read during the t data _ invalid duration. example: configuration registers are set as follows: clk_reg = 8?b0010_0000 dec_reg_r1_i = 0100_0101 dec_reg_r2_i = 1100_0101 fir_ctl_reg_i = 0000_0100 adc is configured to a data rate of 1khz, chop_clk to 2khz, and modulator clock to 1mhz, decimation ratio of cic1 = 64, and dec imation ratio of cic2 = 4. with these settings the various time periods as shown in the figure 16 are as follows: t data _ status _ rd = 100 sec (t data _ status _ rd = (1/mod_clk) * r1 * [((mod_clk/(2*chop_clk))*(1/r1)) - 2.5) t data _ invalid = 8 sec t adc = 1msec t data _ valid = t adc - t data _ invalid = 1msec - 8 sec chop_clk and por_n are internal signals of the device. configure device start adc dvdd/avdd por_n int chop_clk channel data register 0x0000 data1 data2 d1 d2 d3 d4 d1 d2 d3 d4 d1 d2 d3 d4 500s 1.5ms t data_status_rd t data_valid t data_invalid v porhid /v porhia t adc
www.austriamicrosystems.com/AS8510 revision 3.4 39 - 46 AS8510 datasheet - detailed description table 34 provides valid combinations of modulator clock, chopper clock and decimation r1 and the corresponding values of t data _ status _ rd and t adc . 7.9.3 soft-reset using bit d[ 7] of reset register 0x09 it is possible to soft-reset the device by writing ?0? into d[7] bit of reset register at 0x09. on applying soft-reset, the dev ice enters into initialization state and d[7] bit changes back to ?1?. the duration period of initialization is 500sec, and, during this perio d, int pin toggles at the rate of internal low power oscillator. toggling on int during the period of initialization should be ignored in the system. dev ice configuration and activation should be carried out only after the initialization period. see figure 17 for the timing details of the sequence of device initialization on soft-reset. figure 17. AS8510 device initialization sequence at soft-reset table 34. valid combinations of modulator clock, chopper clock and decimation ratio r1 modulator clock chopper frequency chop_clk decimation ratio r1 t data _ status _ rd t adc r2/(2*chop_clk) for r2=4 1mhz 2khz 64 1usec * 64 * [4 - 2.5] = 96usec 1msec 2mhz 2khz 64 0.5usec * 64 * [8 - 2.5] = 176usec 1msec 2mhz 2khz 128 0.5usec * 128 * [4 - 2.5] = 96usec 1msec 2mhz 4khz 64 0.5usec * 64 * [4 - 2.5] = 48usec 0.5msec data-n data-n+1 d4 d1 d2 d3 d4 d1 t data_status_rd t data_valid t data_invalid re-configure device start adc int chop_clk channel data register 0x0000 data1 data2 d1 d2 d3 d4 d1 d2 d3 d4 d1 d2 d3 d4 500s 1.5ms t data_status_rd t data_valid t data_invalid soft reset using d7
www.austriamicrosystems.com/AS8510 revision 3.4 40 - 46 AS8510 datasheet - detailed description 7.9.4 reconfiguring gain setting of pga only pga gain settings can be changed dynamically while adc conversions are in progress. when pga gain settings are changed, th e first sample from the adc is invalid. ignore the first interrupt after the gain re-configuration. valid data starts from the second i nterrupt onwards. figure 18. AS8510 - reconfiguration of gain setting of pga 7.9.5 configuring the de vice during normal mode following registers can be programmed dynamically when the device is in operational mode (normal mode). ach_ctl_reg address is 0x17 pga_ctl_reg address is 0x03 during the operation (normal mode) of the device, if any of the registers need to be programmed or changed other than the above mentioned registers, then it is required to stop the device by writing in to mod_ctl_reg ?stop? bit and configure the device as per the re quirements and start the device. data-n data-n+1 d4 d1 d2 d3 d4 t data_status_rd t data_valid t data_invalid int chop_clk channel data register data1 data2 d2 d3 d4 d1 d2 d3 d4 d1 d2 d3 d4 t data_status_rd t data_valid t data_invalid d1 t data_status_rd gain re-configuration can be carried out in this slot, skip next interrupt and channel data. read channel data in this slot valid data
www.austriamicrosystems.com/AS8510 revision 3.4 41 - 46 AS8510 datasheet - detailed description 7.10 low side current m easurement application figure 19. application diagram AS8510 20 pin (ssop20) vbat_gnd vbat_in ets etr avss avdd vcm ref rshl rshh int clk sdi men chop_clk dvdd dvss sdo sclk cs 100nf 100nf +12v 481r r 12v battery +- 100ohm load 1f 1f c note : on etr connect constant resistor (temp co = 0) on ets connect pt100 3.3v 3.3v
www.austriamicrosystems.com/AS8510 revision 3.4 42 - 46 AS8510 datasheet - package drawings and markings 8 package drawings and markings the product is available in a 20-pin ssop package. figure 20. drawings and dimensions symbol min nom max a- -2.00 a1 0.05 - - a2 1.65 1.75 1.85 b 0.22 - 0.38 c 0.09 - 0.25 d 6.90 7.20 7.50 e 7.40 7.80 8.20 e1 5.00 5.30 5.60 e - 0.65 bsc - l 0.55 0.75 0.95 l1 - 1.25 ref - l2 - 0.25 bsc - r0.09 - - 0o 4o 8o n20 yywwixx AS8510
www.austriamicrosystems.com/AS8510 revision 3.4 43 - 46 AS8510 datasheet - package drawings and markings notes: 1. dimensions & tolerancing conform to asme y14.5m-1994 . 2. all dimensions are in millimeters. angles are in degrees. marking: yywwixx. 8.1 recommended pcb footprint figure 21. pcb footprint yy ww i xx last two digits of the current year manufacturing week assembly plant identifier assembly traceability code recommended footprint data symbol mm a9.02 b6.16 c0.46 d0.65 e6.31
www.austriamicrosystems.com/AS8510 revision 3.4 44 - 46 AS8510 datasheet - revision history revision history note: typos may not be explicitly mentioned under revision history. revision date owner description 1.1 jun 22, 2009 mbr initial version 1.2 dec 02, 2009 ss2, rad updated the datasheet according to 1.8 specification dec 08, 2009 ss2 following modifications carried out in table 27 : 1) deleted max value for parameter ?temperature upper limit? 2) added footnote 2 3) added new parameter ?temperature sensor output (without gain calibration) 1.3 feb 19, 2010 mbr updated table 15 with pga information updated voltage measurement updated v ref and v in values in table 17 and v ref in table 18 inserted new table 28 - system measurement error budget 2.0 june 01, 2010 mbr changed the pin name agnd to vcm current source added in the block diagram added application diagram updated electrical characteristics on page 7 updated detailed system and block specifications on page 9 updated standby mode - power consumption on page 37 3.0 oct 29, 2010 ss2 updates carried out across the datasheet 3.1 nov 02, 2010 ss2 updated ref voltage offset in table 18 3.2 nov 14, 2010 ss2 added sections 7.9.2, 7.9.3, 7.9.4 3.3 nov 26, 2010 vel formatted figures 17, 18 in portrait mode. index modified from page 39 dec 03, 2010 ss2 added configuring the device during normal mode on page 40 3.4 mar 01, 2011 mbr / ss2 updated general description , key features , applications , pin descriptions , current measurement ranges , differential input amplifier for current channel , differential input amplifier for voltage channel , sigma delta analog to digital converter , bandgap reference voltage , system measurement error budget for gains 5 and 25 , package drawings and markings . deleted voltage measurement.
www.austriamicrosystems.com/AS8510 revision 3.4 45 - 46 AS8510 datasheet - ordering information 9 ordering information the devices are available as the standard products shown in table 35 . note: all products are rohs compliant and pb-free. buy our products or get free samples online at icdirect: http://www.austriamicr osystems.com/icdirect technical support is available at http://www.austriamicrosystems.com/technical-support for further information and requests, please contact us mailto: sales@austriamicrosystems.com or find your local distributor at http://www.austriamicros ystems.com/distributor table 35. ordering information ordering code description delivery form package AS8510-asst data acquisition device for ba ttery sensors tape a nd reel 20-pin ssop
www.austriamicrosystems.com/AS8510 revision 3.4 46 - 46 AS8510 datasheet - copyrights copyrights copyright ? 1997-2011, austriamicrosystems ag, tobelbaderstrasse 30, 8141 unterpremstaetten, austria-europe. trademarks registe red ?. all rights reserved. the material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. all products and companies mentioned are trademarks or registered trademarks of their respective companies. disclaimer devices sold by austriamicrosystems ag are covered by the warranty and patent indemnification provisions appearing in its term of sale. austriamicrosystems ag makes no warranty, express, statutory, implied, or by description regarding the information set forth he rein or regarding the freedom of the described devices from patent infringement. au striamicrosystems ag reserves the right to change specificatio ns and prices at any time and without notice. therefore, prior to designing this product into a system, it is necessary to check with austriamic rosystems ag for current information. this product is intended for use in normal commercial applications. applications requiring extended temper ature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by austriamicrosystems ag for each application. for shipments of les s than 100 parts the manufacturing flow might show deviations from the st andard production flow, such as test flow or test location. the information furnished here by austriamicrosystems ag is believed to be correct and accurate. however, austriamicrosystems ag shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. no obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems ag rendering of technical or other services. contact information headquarters austriamicrosystems ag tobelbaderstrasse 30 a-8141 unterpremstaetten, austria tel: +43 (0) 3136 500 0 fax: +43 (0) 3136 525 01 for sales offices, distributors and representatives, please visit: http://www.austriamicrosystems.com/contact

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